DFM requirements for layout
1. The preferred process route has been determined, and all devices have been placed on the board.
2. The coordinate origin is the intersection of the left and lower extension lines of the plate frame, or the lower left pad of the lower left socket.
3. The actual size of PCB and the position of positioner are consistent with the process structural element diagram, and the device layout in the area with limited device height requirements meets the requirements of the structural element diagram.
4. The position of dial switch, reset device and indicator light is appropriate, and the handle bar does not interfere with its surrounding devices.
5. The outer frame of the plate shall be smooth with a radian 197mil, or designed according to the structural dimension drawing.
6. Ordinary plate has 200mil process edge; The process edge reserved on the left and right sides of the backplane is greater than 400mil, and the process edge reserved on the upper and lower sides is greater than 680mil. The device placement does not conflict with the window opening position.
7. All additional holes to be added (ICT positioning hole 125mil, handle bar hole, elliptical hole and optical fiber support hole) are not missing and set correctly.
8. The device pin spacing, device direction, device spacing and device library of wave soldering shall take into account the requirements of wave soldering.
9. The device layout spacing meets the assembly requirements: the surface mount device is greater than 20MIL, the IC is greater than 80mil, and the BGA is greater than 200mil.
10. The distance between the component surface and the crimping part is greater than 120mil, and there is no device in the penetration area of the crimping part on the welding surface.
11. There are no short devices between high devices, and there are no patch devices and short and small plug-in devices within 5mm between devices with a height greater than 10mm.
12. Polarity devices are marked with polarity silk screen. The X and Y directions of polar plug-in components of the same type are the same.
13. All devices are clearly marked without unclear marks such as p *, ref, etc.
14. There are three positioning cursors on the surface containing patch devices, which are placed in an "L" shape. The distance between the positioning cursor center and the board edge is greater than 240mil.
15. If it is necessary to conduct panel assembly, the layout shall be convenient for panel assembly and PCB processing and assembly.
16. The notched plate edge (special-shaped edge) shall be filled by milling groove and stamp hole. The stamp hole is non-metallic hollow, generally with a diameter of 40mil and an edge distance of 16mil.
17. The test points for debugging have been added in the schematic diagram, and the position in the layout is appropriate.
Thermal design requirements for layout
18. The heating elements and exposed parts of the shell shall not be close to the wires and thermal elements, and other parts shall also be properly away from them.
19. Considering the convection problem, the radiator is placed without high device interference in the projection area of the radiator, and the range is marked on the installation surface with silk screen.
20. The reasonable and smooth heat dissipation channel shall be considered in the layout.
21. The electrolytic capacitor shall be properly separated from the high heat device.
22. Consider the heat dissipation of high-power devices and devices under the gusset plate.
Signal integrity requirements for layout
23. The starting end is matched close to the transmitting device, and the terminal is matched close to the receiving device.
24. The decoupling capacitor shall be placed close to relevant devices
25. The crystal, crystal oscillator and clock driving chip are placed close to relevant devices.
26. High speed and low speed, digital and analog are arranged separately according to modules.
27. Determine the bus topology according to the analysis and simulation results or existing experience to ensure that the system requirements are met.
28. If it is a modified board design, simulate and give a solution in combination with the signal integrity problem reflected in the test report.
29. The layout of the synchronous clock bus system meets the timing requirements.
30. Inductive devices prone to magnetic field coupling such as inductance, relay and transformer shall not be placed close to each other. When there are multiple inductive coils, the direction is vertical and uncoupled.
31. In order to avoid electromagnetic interference between devices on the welding surface of single board and adjacent single boards, sensitive devices and strong radiation devices shall not be placed on the welding surface of single board.
32. The interface devices are placed close to the board edge, and appropriate EMC protection measures have been taken (such as shielding shell, power ground hollowing, etc.) to improve the EMC capacity of the design.
33. The protection circuit shall be placed near the interface circuit, following the principle of protection before filtering.
34. Devices with large transmission power or particularly sensitive (such as crystal oscillator, crystal, etc.) are more than 500mil away from the shield and shield shell.
35. A 0.1uF capacitor is placed near the reset line of the reset switch to keep the reset device and reset signal away from other strong interference devices and signals.
Layer setting and power ground separation requirements
37. Vertical wiring rules shall be defined when two signal layers are directly adjacent.
38. The main power layer shall be adjacent to its corresponding stratum as far as possible, and the power layer shall meet the 20h rule.
39. Each wiring layer has a complete reference plane.
40. Multilayer plates are stacked and the core material (core) is symmetrical to prevent warpage caused by uneven density distribution of copper sheet and asymmetric medium thickness.
41. The plate thickness shall not exceed 4.5mm. If the plate thickness is greater than 2.5mm (the back plate is greater than 3mm), the process personnel shall confirm that there are no problems in PCB processing, assembly and equipment, and the thickness of PC card is 1.6mm.
42. When the thickness diameter ratio of the via is greater than 10:1, it shall be confirmed by the PCB manufacturer.
43. The power and ground of the optical module are separated from other power and ground to reduce interference.
44. The power supply and ground treatment of key devices meet the requirements.
45. When there are impedance control requirements, the layer setting parameters meet the requirements.
Power module requirements
46. The layout of the power supply part ensures that the input and output lines are smooth and not crossed.
47. When the single board supplies power to the gusset board, the corresponding filter circuit has been placed nearby at the power outlet of the single board and the power inlet of the gusset board.
48. Considering the smooth overall routing, the main data flow direction is reasonable.
49. Adjust the pin allocation of drain resistance, FPGA, EPLD, bus driver and other devices according to the layout results to optimize the wiring.
50. In the layout, the space at the dense routing shall be appropriately increased to avoid the situation that it cannot be arranged.
51. If special materials, special devices (such as 0.5mmbga) and special processes are adopted, the delivery time and processability have been fully considered and confirmed by PCB manufacturers and process personnel.
52. The pin correspondence of gusset connector has been confirmed to prevent the direction and orientation of gusset connector from being reversed.
53. If there are ICT test requirements, the feasibility of adding ICT test points shall be considered in the layout to avoid the difficulty of adding test points in the wiring stage.
54. When the high-speed optical module is included, the optical port transceiver circuit shall be given priority in the layout.
55. After the layout is completed, a 1:1 assembly drawing has been provided for the project personnel to check whether the device packaging selection is correct according to the device entity.
56. The inner plane has been considered to shrink inward at the window opening, and a suitable no wiring area has been set.